Article ID: 000079214 Content Type: Troubleshooting Last Reviewed: 11/23/2011

Stratix V QDR II and QDR II SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY Memory Interfaces May Exhibit Write Timing Failure

Environment

Quartus Edition

Quartus® II Subscription Edition

Version Found: 11.0 Version Fixed: 12.0

FPGA Intellectual Property

Nios® II Processor

Version Found: 11.0 Version Fixed: 12.0

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

Memory interfaces targeting Stratix V devices may exhibit write setup or write hold timing failures.

Resolution

A workaround for interfaces running at 400MHz or slower is to enable the high-performance Nios II-based sequencer instead of the RTL-based sequencer.

All postings and use of the content on this site are subject to Intel.com Terms of Use.