Article ID: 000079213 Content Type: Product Information & Documentation Last Reviewed: 10/10/2013

How do I connect the signals of the ALTDQ_DQS2 Hard Read FIFO?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The ALTDQ_DQS2 Hard Read FIFO has the following ports as described below:

lfifo_rden: Data input to the Read FIFO Read Enable. This signal is the full read enable token generated by user logic and is asserted for the length of the desired read burst.

rfifo_reset_n: Active low reset to the Read FIFO.

vfifo_qvld: This signal is used as the write enable on the Read FIFO in all cases where the capture strobe is not bidirectional.

 

Related Products

This article applies to 11 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Cyclone® V SE SoC FPGA

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.