Article ID: 000079186 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Are there any guidelines on how to use the rx_dpa_hold signal in the altlvds_rx megafunction?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, the rx_dpa_hold port can be used to lock the DPA in its current position when there is an extended run length of data with no transitions.  In order for the DPA circuit to function properly, the DPA run length specification cannot be violated.  Refer to the respective device Datasheet for the DPA run length specification.

For example, in the following situation, a link needs to be established where the transmitter sends a 0xBCBC training pattern but after the receiver has achieved lock, the transmitter may send a very long run of "1111...".

In order for the DPA not to get out of lock when actual data is being sent again you can use rx_dpa_hold to keep the DPA phase selected when sending a repeated pattern of 11111's or 00000's.

To use the rx_dpa_hold input port, follow these steps:

1) Assert rx_dpa_hold after first training the link, this will lock the DPA to a known good phase

2) You can now send static data, either constant 1's or constant 0's

3) When you are ready to send toggling data, de-assert rx_dpa_hold

If the phase between the data input and input clock changes, after the de-assertion of  rx_dpa_hold, the DPA will hunt for a new optimum phase.

Related Products

This article applies to 4 products

Stratix® III FPGAs
Stratix® IV GX FPGA
Stratix® IV E FPGA
Stratix® FPGAs