Description
Due to a problem in the Quartus® II software version 11.1 SP2 and earlier, this error may be generated during synthesis if your HDL code include bit string literals in VHDL-2008 format.
For example, the following code may generate the above error:
constant CSR : std_logic_vector(4 downto 0) := 5d"0";
Resolution
To work around this problem, avoid using VHDL-2008 bit string literals. For example, replace the above code with:
constant CSR : std_logic_vector(4 downto 0) := “00000”;
This problem is fixed beginning with the Quartus II software version 12.0.