Article ID: 000079169 Content Type: Troubleshooting Last Reviewed: 03/15/2023

Why is the input data rate parameter text box not present in the ALTLVDS_RX Intel® FPGA IP in the Quartus® II software version 13.0sp1?

Environment

    ALTLVDS_RX
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

In the Quartus® II software version 13.0, the input data rate text box was available when using external phase-locked lioop (PLL) mode with DPA enabled in the ALTLVDS_RX Intel® FPGA IP.

 

Resolution

Beginning with version 13.0sp1, the fitter automatically derives the data rate from the associated PLL Intel FPGA IP settings. 

Related Products

This article applies to 8 products

Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Stratix® V GS FPGA
Stratix® V E FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.