How can I compile both VHDL and Verilog simulation libraries for NC-Sim?

Due to a problem in the Quartus® II software, using the EDA Simulation Library Compiler to compile both Verilog HDL and VHDL simulation libraries for NC-Sim to the same output directory overwrites the file cds.lib. No other files and subdirectories are affected.

To work around this problem, follow the steps below.

1. Compile the Verilog HDL libraries
2. Copy the file cds.lib in the output directory to another location
3. Compile the VHDL libraries in the same output directory as the Verilog HDL libraries
4. Edit the cds.lib file which was just generated and append the contents of the first cds.lib except for the first line that begins with
    
    include ...

This problem is scheduled to be fixed in a future release of the Quartus II software.