Article ID: 000079154 Content Type: Troubleshooting Last Reviewed: 08/23/2012

Why does my Stratix IV design have high BER on a PMA Direct transmit interface?


  • Stratix® IV GX FPGA
  • Stratix® IV GT FPGA
  • Quartus® II Subscription Edition

    In the Quartus® II software version 11.1 SP2 and earlier, incorrect timing models for PMA Direct transmit interfaces may result in hardware errors such as increased bit error rates (BER) for designs targeting Stratix® IV devices. In particular, these incorrect models affect designs that have low timing margin on the affected timing path, especially at high temperature and low core voltage.

    The issue affects only designs that use the ALTGX megafunction transceiver in Basic (PMA Direct) mode in the transmitter. This mode uses a direct core-to-PMA register transfer on the transmit side, instead of using the hard PCS logic and phase-compensation FIFO.

    Beginning with the Quartus II software version 12.0, the Stratix IV timing model has changed to update the delay model for PMA Direct transceiver interfaces. If your design uses earlier versions of the Quartus II software, you should upgrade to version 12.0 or later, or constrain the design to match the updated timing model as explained in detail below.


    To ensure correct behavior over full PVT range, the Quartus II software version 12.0 adds the following additional delay amounts to the core-to-PMA timing path:

    • 550 ps delay in Stratix IV 530 and 360 density ranges
    • 350 ps delay in Stratix IV 230 and 110 density ranges

    To use the corrected timing models, perform timing analysis, in the Quartus II software version 12.0 or above. PMA Direct timing will be modeled correctly for all timing corners. Note that timing closure may be more difficult with the newer models.

    If you are unable to migrate your design to the Quartus II software version 12.0, add clock uncertainty constraints to represent the timing model change. Download and run the PMA Direct Timing Evaluation Script to specify the required constraints. The script checks timing slack on the affected interfaces, and provides Synopsys Design Constraint (SDC) commands to add clock uncertainty constraints in versions 11.1 SP2 and earlier.

    To run the PMA Direct Timing Evaluation Script, use the following command from the command line after compiling the design:

    quartus_sta –t stratixiv_pma_direct_timing_evaluation.tcl –project <project name>

    The PMA Direct interface timing performance is affected by the device core voltage. If you have good minimum voltage control and/or run at elevated core voltage, you can achieve better performance than the worst case numbers in the Quartus II timing model. The script provides an option to pro-rate the timing model based on elevated VCC core voltage for better timing performance.

    To use pro-rated timing model information, add the following script option:

    -core_voltage <voltage in V>

    For Stratix IV GX devices, pro-rating data is available for 0.90 or 0.92 V. For Stratix IV GT devices, you can enter the normal nominal core voltage 0.95 to get available pro-rating data that is not included in the Quartus II timing model. You can use the PMA Direct Timing Evaluation Script to provide pro-rating constraints in any Quartus II version.

    To address challenges meeting timing, you may need to make placement constraints to optimize TX core registers placement. Refer to the related solution below for more information on making placement constraints.



    All postings and use of the content on this site are subject to Terms of Use.