Article ID: 000079144 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What should I do to avoid the VHDL Altmemphy or DDR/DDR2 High Performance controller simulation failure giving the error "Iteration limit reached" or "Failure: -- SIMULATION FAILED" in Stratix® III and Cyclone® III devices when generating the design?



This issue has been fixed in Quartus II software version 7.2 Service Pack 1(SP1).


If you are simulating a VHDL instance of the ALTMEMPHY or the DDR or DDR2 SDRAM High Performance Controllers, you may receive an "Iteration limit reached" or “Failure: --- SIMULATION FAILED“ error message and you will then be unable to correctly simulate your system. This sometimes occurs with Stratix III or Cyclone III devices, but does not occur with Stratix II, HardCopy® II, Arria® GX or Stratix II GX devices.  To resolve this error, you will need to fix the ALTMEMPHY VHDL simulation netlist as follows:

1. Locate the directory which contains your <phy_name>_phy.vho file, this file will be found in the directory in which you created the ALTMEMPHY Megafunction, and this directory contains all the HDL files required.

2. Download the file attached with this solution and copy it to any suitable path on your computer.  This path shall be referred to in the following instructions as <path_to_tribus_del>.


Click here to download file.


3. From a command window or shell (Windows users select Start> All Programs> Accessories> Command Prompt), change directory to the one which contains your <phy_name>_phy.vho file.  This should be found in the directory in which you created the DDR or DDR2 SDRAM High Performance Controllers or ALTMEMPHY Megafunction. 


4. Ensure that you have PERL installed on your computer and accessible via your search path.  (Windows users may wish to install PERL from or  Linux users will probably have PERL included with their distribution).


5. Run the script with :


For CIII designs :  >perl -f <path_to_tribus_del>/     <phy_name>_phy.vho

For SIII designs :  >perl -f <path_to_tribus_del>/ -d <phy_name>_phy.vho

6. The script will run, producing some output (and will make a .bak copy of the .vho should that be required) which will end with a report similar to :

[tribus_del] tribus_del terminated successfully:

[tribus_del] 12 instances found.

[tribus_del] 21 string substitutions made.

The exact numbers will depend upon the width of your memory interface and number of clocks. The number of tri_bus instances is given by :

Number of DQ pins Number of DQS pins Number of DQSN pins Number of MEM_CLK pins Number of MEM_CLK_N pins

The number of string substitutions should be between one or two times the number of tri_bus instances.

7. Now re-run your simulation, which should now pick up the new <phy_name>_phy.vho file and run successfully.

Related Products

This article applies to 2 products

Cyclone® III FPGAs
Stratix® III FPGAs



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