When simulating the Altera® Hard IP for PCI Express® as endpoints with third-party BFMs, a simulation error may be reported for the time between sending out EIOS and entering Electrical Idle.
An example Denali BFM error for this case is shown below:
*Denali* Error: <sword_tb.ep1>@42853200 ps :: Detected[cfg_0_0] (TX)  PL_TTX_IDLE_SET_TO_IDLE [PCISIG]. [port_0].TX: Transmitter exceeded TTX-IDLE-SET-TO-IDLE (20 Gen1-UI).
This issue only affects simulation and has no impact on hardware.
The root cause is due to transciever simulation model analog PMA timing inaccuracies.
Modify the file altera_xcvr_fpll_a10.sv to add a timescale as shown below:
3. Save and recompile your simulation