Qsys (Beta) does not support all legacy SOPC Builder PLL components

Qsys does not support legacy SOPC Builder PLL components, except those with an input frequency of 50 MHz. Generating a design that includes a legacy PLL with an input frequency not set to 50 MHz fails with an error similar to the following:

Error: altera_avalon_pll_khh3cm2h: CLock yyclock_inclk0 of frequency 50.000 MHz driving the PLL module conflicts with the PLL inclock of frequency 125.000 MHz.

If you want to configure a PLL with an input frequency other than 50 MHz, replace the SOPC Builder PLL with an Avalon ALTPLL.