Incorrect Pin Mapping for DDR3 LRDIMM and LPDDR3 in Arria 10 EMIF

This problem affects DDR3 LRDIMM and LPDDR3 interfaces on Arria 10 devices.

DDR3 LRDIMM

For DDR3 LRDIMM interfaces that employ the DDR3 Scheme 5: LRDIMM address/command pin mapping scheme, the IP incorrectly assigns pins to pin indexes within an I/O bank as follows:

The above pin-to-pin-index assignments are incorrect. The correct assignments are as follows:

LPDDR3

For LPDDR3 interfaces that employ the LPDDR3 Scheme 1 address/command pin mapping scheme, the IP incorrectly assigns pins to pin indexes within an I/O bank as follows:

The above pin-to-pin-index assignment are incorrect. The correct assignments are as follows:

The workaround for this issue is to apply the correct pin assignments.

This issue is fixed in version 15.1.