When you generate a Qsys system that contains the Serial RapidIO® IP, Qsys generates a (.tcl) script and Synopsys Design Constraint(.sdc) file for your IP.
The .sdc file does not work correctly when there are multiple instances of the Serial RapidIO IP present in your Qsys system. The problem is that the create_generated_clock statements match more than one clock, and fail. You will see these in the ignored constraints report within the TimeQuest™ Timing Analyzer.
To work around this problem, make a copy of the create_generated_clock statements for each instance of the Serial RapidIO IP, then change the names of the clocks so that they are unique and modify the source and target filters so that they include the instance name.
For example change this:
create_generated_clock -name clk_div_by_two_rio_blocks_rapidio_3 -source [get_nets *rio_blocks_rapidio_3_rio_inst*tx_clkout] -divide_by 2 [get_nets *rio_blocks_rapidio_3*riophy_xcvr|clk_div_by_two]
create_generated_clock -name clk_div_by_two_rio_blocks_rapidio_3_myinst -source [get_nets *my_inst*rio_blocks_rapidio_3_rio_inst*tx_clkout] -divide_by 2 [get_nets *my_inst*rio_blocks_rapidio_3*riophy_xcvr|clk_div_by_two]
This problem is scheduled to be fixed in a future version of the Quartus® II software.