How do I simulate the Intel® Arria® 10, Arria® V GZ, and Stratix® V PCI Express IP cores in 3.0 PIPE mode?

Due to a problem in the Quartus® II software and the Intel® Quartus® Prime Software versions, the Intel® Arria® 10, Arria® V GZ, and Stratix® V Hard IP for PCI Express IP cores only support 3.0 PIPE simulation using the Synopsys (VCS) simulator. To use other simulators, follow the instructions in the Resolution section.

To work around this problem, follow these steps:

1. Replace the existing files under ...\simulation\submodules with these versions:
   • altpcietb_pipe32_driver.v
   • altpcietb_pipe32_hip_interface.v
2. Edit the`defines in each of those files to match your design hierarchy:
   • In altpcietb_pipe32_hip_interface.v, replace top_tb.top_inst with your hierarchy:
     define HIP_INTERFACE top_tb.dut_pcie_tb.g_altpcie_hip_pipe32_sim_probe.altpcietb_pipe32_hip_interface
3. In the top-level testbench file (top_tb in this example), edit the dut_pcie_tb instantiation and set the following parameters:
   • serial_sim_hwtcl                     (0),
   • enable_pipe32_sim_hwtcl              (1),
   • enable_pipe32_phyip_ser_driver_hwtcl (1)

This problem is not scheduled to be fixed in a future release of the Intel® Quartus® Prime Software or Quartus® II software.