Why do I get the following warnings when using the RLDRAM II Megacore?
Warning: Atom "top_controller_wrapper:top_controller|top_controller_auk_rldramii_datapath:rldramii_io|top_controller_auk_rldramii_dqs_group:auk_rldramii_dqs_group_0|dqs_io~regout" has port REGOUT that should be connected in DDIO input and bidirectional modes
Warning: Atom "top_controller_wrapper:top_controller|top_controller_auk_rldramii_datapath:rldramii_io|top_controller_auk_rldramii_qvld_group:auk_rldramii_qvld_group_0|qvld_capture~regout" has port REGOUT that should be connected in DDIO input and bidirectional modes
Warning: DQ I/O pins fed by DQS I/O pin "top_rldramii_qk" have different Output Enables -- all DQ I/O pins fed by the same DQS I/O pin should have the same Output Enable signalInfo: I/O pin
The RLDRAM II megacore uses Stratix® II IO WYSIWYGs to create DDIO functionality. Stratix II IO WYSIWYGs are used to generate DQ pins, DQS delay elements, and the QVLD capture. These warnings are meant to inform the user that some IO WYSIWYGs ports are not connected. This is due to mode in which the IO WYSIWYG is being used by design and can be safely ignored.
The information message in the third warning above is also by design. QVLD is captured using the same delayed DQS signal used to capture the DQs, thus Quartus® II software considers QVLD to be the same pin type as the DQ pins. QVLD is an input to the device, so the output enable is permanently tied low. However, the DQ OE constantly toggles. Quartus II is stating that the QVLD OE should be toggling because it thinks QVLD is a data pin. This can be safely ignored.