Due to a problem with the AVMM-DMA variant of the Hard IP for PCI® Express core, you may see data corruption or descriptors that never complete (Done bit is never set). This only affects designs using an External DMA Descriptor Controller, the internally instantiated controller design is fully functional.
This problem may be sporadic, and may only occur when a large number of descriptors are programmed back-to-back.
Author's note: this can be worked around, but it requires editing a file in the Quartus install, which I don't think we want to recommend.
This behavior is caused by incorrect setting of the ready latencies of the dma_rd_master and dma_wr_master descriptor programming interfaces.
These are shown as the rd_ast_rx and rd_ast_tx interfaces in the "Avalon-MM DMA Block Diagram with External DMA Descriptor Contoller" figure in the user guide, and specifically as RdAstRxReady_o, WrAstTxReady_o in the "Descriptor Instruction Interface from Descriptor Controller to Read (Write) DMA Engine" tables.
The ready latency on these signals is incorrectly set to 0, when the correct value should be 3.
This problem is scheduled to be fixed in a future release of the Quartus® Prime software.