Article ID: 000078983 Content Type: Troubleshooting Last Reviewed: 05/23/2016

What are the Native PHY IP to FPGA fabric clock frequencies of the Arria 10 device when configured for PCI Express Gen1, Gen2, or Gen3 PIPE?

Environment

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Description

For PCI Express Gen1 PIPE, the Arria® 10 device Native PHY IP FPGA fabric clock frequency is:

  • 250 MHz if the byte serializer and deserializer are disabled
  • 125 MHz if the byte serializer and deserializer are set to x2

For PCI Express Gen2 PIPE, the Arria 10 device Native PHY IP FPGA fabric clock frequency is:

  • 125 MHz if the lane data rate is set to Gen1 (2500 Mbps)
  • 250 MHz if the lane data rate is set to Gen2 (5000 Mbps)

For PCI Express Gen3 PIPE, refer to the "PIPE Gen3 32 bit PCS Clock Rates" table in the Arria 10 Transceiver PHY User Guide (PDF).

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