The Stratix® V Hard IP for PCI Express® requests the link partners to transmit Gen 3 data using either preset 7 or preset 8 by default. Depending on the channel characteristics, using preset 9 for the Hard IP requesting preset along with full bandwidth for the gain peaking frequency of the equalizer may provide better eye margin at the Hard IP receiver.
Follow the steps below to implement the work around.
a) To modify the Hard IP RTL to request its link partner to transmit with Gen3 preset 9, follow the steps below.
1. Edit the generated altpcie_sv_hip_ast_hwtcl.v file located in <generated_ip_dir>\top\synthesis\submodule\
2. Change the following lines from:
localparam [17:0]gen3_coeff_1 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_1_hwtcl [17:0]: 18\'h7;
localparam [17:0]gen3_coeff_2 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_2_hwtcl [17:0]: 18\'h8;
localparam [17:0]gen3_coeff_3 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_3_hwtcl [17:0]: 18\'h7;
localparam [17:0]gen3_coeff_4 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_4_hwtcl [17:0]: 18\'h8;
To
localparam [17:0]gen3_coeff_1 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_1_hwtcl [17:0]: 18\'h9;
localparam [17:0]gen3_coeff_2 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_2_hwtcl [17:0]: 18\'h9;
localparam [17:0]gen3_coeff_3 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_3_hwtcl [17:0]: 18\'h9;
localparam [17:0]gen3_coeff_4 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_4_hwtcl [17:0]: 18\'h9;
b) Add the assignment below for each transceiver pin for the PCIe IP you are targeting with this change.
set_instance_assignment -name XCVR_RX_EQ_BW_SEL BW_FULL_12P5 –to <txvr_rx_data_pin_N>