Article ID: 000078969 Content Type: Troubleshooting Last Reviewed: 01/23/2015

Why do I see an incorrect tx_outclock frequency when simulating the Altera Soft LVDS IP with MAX 10 devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a known issue in Quartus® II software versions 14.1 and earlier, you may see an incorrect tx_outclock frequency when simulating the Altera® Soft LVDS IP with MAX® 10 devices.

     

    Resolution

    This known problem only affects simulation behaviour, and is scheduled to be fixed in future version of the Quartus II software.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.