Article ID: 000078969 Content Type: Troubleshooting Last Reviewed: 04/24/2023

Why do I see an incorrect tx_outclock frequency when simulating the Altera Soft LVDS IP with MAX®10 devices?

Environment

  • Quartus® II Subscription Edition
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    Description

    Due to a known issue in Quartus® II software versions 14.1 and earlier, you may see an incorrect tx_outclock frequency when simulating the Altera® Soft LVDS IP with MAX® 10 devices.

     

    Resolution

    This known problem only affects simulation behaviour

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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