Article ID: 000078964 Content Type: Troubleshooting Last Reviewed: 05/18/2013

Possible Enumeration Failure for Arria V GZ Hard IP for PCI Express Gen3 x8

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

Gen 3 x8 variants of the Arria V GZ Hard IP for PCI Express IP Core may fail during enumeration when the adaptive equalization (AEQ) is active during the LTSSM speed change state.

Resolution

This issue is fixed in version 12.1 SP1 of the Arria V GZ Hard IP for PCI Express IP Core.

Related Products

This article applies to 1 products

Arria® V GZ FPGA

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