Article ID: 000078961 Content Type: Product Information & Documentation Last Reviewed: 04/25/2014

How should the DCLK and DATA pins be connected when using the HPS to configure the FPGA fabric in Arria V or Cyclone V SoC devices?

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Description

When configuring an Arria® V SoC or Cyclone® V SoC device through the HPS, the configuration DATA pins can be left unconnected. The DCLK pin should not be left unconnected and should be connected to either VCCPGM or GND assuming this pin is not used for device initialization.

Resolution

 

Related Products

This article applies to 5 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA

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