VHDL designs that target Stratix V devices cannot be simulated by the ModelSim-Altera Starter Edition software versions 6.6c and 6.6d

Due to a problem in the ModelSim-Altera Starter Edition software version 6.6c and 6.6d, designs in VHDL that target Stratix V devices cannot be simulated. This problem does not affect the ModelSim-Altera Edition software.Due to this problem, you may see errors similar to the following:

# ALTERA version supports only a single HDL # ** Fatal: (vsim-3512) Instantiation of "stratixv_ds_coef_sel" failed. Unable to check out Verilog simulation license.

Simulate the design with Verilog HDL or use the ModelSim-Altera Edition software version 6.6d.