Why is timing performance degraded for Qsys-generated logic in the Quartus II software version 13.0 compared with earlier versions?

Due to an issue in the Quartus® II software version version 13.0,  there is a possibility that the timing will be degraded if the system has width adapters in the generated synthesis HDL files when Qsys systems are migrated to the newer version. This performance degradation is due to an issue in the width adapter interconnect IP logic.

To avoid this issue, upgrade to the Quartus II software version 13.0 SP1 where the issue has been fixed. Reopen your Qsys system, upgrade the interconnect IP, and regenerate the synthesis HDL.