Article ID: 000078919 Content Type: Troubleshooting Last Reviewed: 04/06/2023

When using the Low Latency 40- and 100-Gbps Ethernet MAC and PHY, is it possible that both the start of packet and end of packet signals assert in the same clock cycle?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, when fragmented or short frames are received, the Low Latency 40- and 100-Gbps Ethernet MAC and PHY Intel® FPGA IP may assert both start of packet (l<n>_rx_startofpacket/dout_sop) and end of packet  (l<n>_rx_endofpacket/dout_eop) signals in the same clock cycle .

Resolution

N/A

Related Products

This article applies to 6 products

Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

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