Memory Timing Violation During Activate Read Auto-Precharge to Refresh/Activate

For designs created in a version of the high-performance controller (HPC) earlier than version 11.0, memory timing violation may occur during the activate to read precharge. Your design may fail to simulate.

For designs targeting 1066 specification and running with 533 MHz speed, increase one control clock cycle of the timing parameters tRP and tRCD, so that the tRC for the controller is greater than the tRC for the memory model.

For designs targeting 1066 specification and running with 400 MHz speed, increase one control clock cycle of the timing parameter tRP, so that the tRC for the controller is greater than the tRC for the memory model.