Article ID: 000078826 Content Type: Product Information & Documentation Last Reviewed: 03/16/2023

How should I connect the refclk and adjpllin ports in the PLL Intel® FPGA IP when using the dedicated cascade path?

Environment

  • Quartus® II Subscription Edition
  • Avalon ALTPLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    There are two reference clock inputs (refclk and adjpllin) when the PLL Intel® FPGA IP is configured with the Cascade Downstream PLL option enabled. 

     

    Resolution

    You need to connect the upstream "Cascade out" signal to the adjpllin input port and you can leave the refclk input unconnected. 

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