Article ID: 000078806 Content Type: Troubleshooting Last Reviewed: 10/04/2016

Are the sts_err_addr* and the sts_corr_dropped_addr registers supported by the Arria 10 EMIF (non-HPS) ECC-related MMR registers?

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Description

Yes, the sts_err_addr* and the sts_corr_dropped_addr registers are supported.

At MMR register address 145, the sts_err_addr* is a 32-bit register and is the address of the most recent single-bit error (SBE) or double-bit error (DBE).
At MMR register address 146, the sts_corr_dropped_addr is a 32-bit register and is the address of the most recent correction command dropped.

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