Inverted clock analysis depends on how the inverted clock is implemented in your design. The following paragraphs describe the two possible implementations:
Case 1: The original non-inverted clock is routed throughout your design and the clock inversion takes place locally (in each logic element or adaptive logic module) for all registers using the negative edge of the clock. In this case, the Quartus® II software does take into account the inverted clock when calculating the clock fmax.
Case 2: In cases where the inversion cannot occur locally, an inverted version of the clock is routed to feed registers using the negative edge of the clock. In this case, the Quartus II software analyzes all registers as though they use the positive edge of the clock. You must make assignments so that the software analyzes the inverted clock correctly. In the TimeQuest Timing Analyzer, create a derived clock and apply it to the output of the logic that performs the inversion. Specify this clock as an inverted clock by checking Invert base clock in the TimeQuest Create generated clock dialog box, or using the SDC -invert option. In the Classic Timing Analyzer, use the Assignment Editor to apply the Inverted Clock assignment to the registers fed by the inverted clock.
For more information about timing analysis, refer to the Quartus II TimeQuest Timing Analyzer (PDF) or Quartus II Classic Timing Analyzer (PDF) chapter in volume 3 of the Quartus II Handbook.