Article ID: 000078791 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get the message "Warning: Compensate clock of PLL pll_inst|altpll:altpll_component|pll has been set to extclk1" when using external feedback mode and my compensation is set for extclk0?


  • PLL
    Description You might get the warning in the Quartus® II software version 3.0 under the following conditions:

    1. External feedback mode is selected and the internal clock ports (C0-C5) are not connected.
    2. Extclk1 has more fanout than the Extclk0 port, which is selected as the clock to be compensated for.

    If both conditions are true, then the external clock compensation is moved from extclk0 to extclk1. However, this change does not affect the actual compensation of the PLL. When the PLL is in External Feedback mode, the compensation is identical between the extclk ports regardless of which extclk port is being compensated.

    The Quartus II fitter incorrectly moves the compensation clock without checking for the extfeedback mode. As a result, the Quartus II software selects the default port of clk0 as being compensated. Since that port is not connected, the software selects the port with the highest fanout (extclk1 has more fanout than extclk0) to compensate and changes it to that port.

    This will be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 1 products

    Stratix® FPGAs



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