Article ID: 000078786 Content Type: Troubleshooting Last Reviewed: 11/30/2015

RapidIO IP Core Arria V GZ Variations Generate an Incorrect SDC File in Qsys

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

If you generate a RapidIO IP core instance in Qsys, and specify target device family Arria V GZ, your RapidIO IP core generates an incorrect SDC file. The file specifies a clock connection to an invalid clock.

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