This problem occurs when the Quartus® II software beginning with version 6.0 performs certain optimizations while extracting state machines. The Quartus II software generates Finite State Machine files (.fsm) for the Conformal software to interpret state machine encoding. The FSM files are generated before state machine optimizations are performed. When certain state optimizations occur after the FSM file is generated, the difference in state machine encoding results in a mismatch between the golden design and the revised design, halting formal verification.
To avoid this problem, turn off Extract Verilog State Machines or Extract VHDL State Machines under More Settings in the Analysis and Synthesis page of the Settings dialog box. Note that depending on the design, turning off state machine extraction might reduce the area/timing performance.