Article ID: 000078731 Content Type: Troubleshooting Last Reviewed: 09/10/2018

Why do I receive incorrect data returned from my read TLP requests on my Intel® Avalon®-Memory Mapped 128 bit Hard IP for PCI* Express?

Environment

    Intel® Quartus® Prime Pro Edition
    Avalon-MM Stratix® V Hard IP for PCI Express Intel® FPGA IP
    Avalon-MM Arria® V Hard IP for PCI Express Intel® FPGA IP
    Avalon-MM Arria® V GZ Hard IP for PCI Express Intel® FPGA IP
    Avalon-MM Cyclone® V Hard IP for PCI Express Intel® FPGA IP
    Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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Description

Due to a problem with the Intel® Quartus® II and Prime software versions 15.0, 16.0, 16.1, 17.0 and 17.1 you may see incorrect read data when the PCI* Express link is highly utilized and there are a lot of out-of-order completions.  This problem only occurs for PCI* Express Hard IP Avalon®-Memory Mapped 128 bit variants.

When this happens, parts of data from incoming reads may appear in the middle of data from a previous read.

Resolution

This problem is caused by the memory holding the completion buffer being sized too small.

To workaround this issue follow these steps:

  1. Look in the generated file directories for the file altpciexpav128_rx.v.
  2. Find the line localparam CB_RX_CPL_BUFFER_DEPTH =256;
  3. Change the line to localparam CB_RX_CPL_BUFFER_DEPTH =512;
  4. Find the lines “wire[7:0] cplram_wraddr;” and “wire [7:0] cplram_rdaddr;”
  5. Change the wire width from 8-bit to 9-bit:
    1. wire  [8:0]      cplram_wraddr;
    2. wire  [8:0]      cplram_rdaddr;”

Version Found: 15.0 and 16.0 to 17.1.1
Version Fixed: 15.1 and 18.0
This issue has been fixed starting in software version 18.0.

Related Products

This article applies to 15 products

Cyclone® V GT FPGA
Arria® V GT FPGA
Cyclone® V GX FPGA
Arria® V GX FPGA
Intel® Arria® 10 GT FPGA
Stratix® V GX FPGA
Arria® V GZ FPGA
Cyclone® V SX SoC FPGA
Arria® V SX SoC FPGA
Intel® Arria® 10 SX SoC FPGA
Arria® V ST SoC FPGA
Cyclone® V ST SoC FPGA
Intel® Arria® 10 GX FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA

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