Stratix V and Arria V GZ Hard IP for PCIe RX Burst Master May Return Completions with Incorrect Traffic Class

The Stratix V and Arria V GZ Hard IP for PCIe RX Burst Master may return completions with incorrect traffic class and attribute fields set.

The workaround is to correct the following RTL file, <install_dir>/ip/altera_pcie/altera_pcie_hip_256_avmm/rtl/altpcieav_dma_hprxm_rdwr.sv. You must add registers to record the correct traffic class.

After: logic [2:0] rd_tc;

Add: logic [1:0] rd_attr_reg;

Add: logic [2:0] rd_tc_reg;

Before the assignment statement:

req_id_reg <= req_id;

Add:

rd_attr_reg <= rd_attr;

rd_tc_reg <= rd_tc;

Under ///RXM Pending Read Interface change the first assignment statement to the following:

assign PndgRdHeader_o = {1\'b0, 4\'hF, rd_tc_reg, rd_attr_reg, 4\'hF, rx_dwlen_reg, req_id_reg[15:0], 1\'b0, rx_addr_reg[6:0], rd_tag_reg};

In <install_dir>/ip/altera_pcie/altera_pcie_hip_256_avmm/rtl/altpcieav_dma_hprxm_cpl.sv, the statement :

assign attr PndRdFifoData_i[48:47];

should read:

assign attr PndRdFifoData_i[47:46];

This issue is fixed in version 14.1 of the Quartus II software.