Due to a problem in the Quartus® II software version 12.0 and later, the simulation models for the PLL_RECONFIG Intel FPGA IP do not accurately show the behavior when the mgmt_reset signal is used. When asserted, the mgmt_reset signal in simulation fails to restore the PLL to its initial parameter settings which were set with the FPGA configuration file.
For example, if you reconfigure the PLL with invalid parameters, the PLL may lose lock. Once in a loss of lock condition, the reconfiguration controller does not accept mgmt_write commands, the status register indicates a busy state, and the mgmt_waitrequest signal is asserted. The only way to recover the PLL from this condition is to assert the mgmt_reset signal to restore the original PLL settings.
The ability for the mgmt_reset signal to restore the PLL original settings is currently not included in the simulation models.
This problem is fixed starting with the Intel® Quartus® Prime Pro or Standard Edition Software version 13.0 .