Description
Altera® does not specify output jitter for fast PLLs on either Stratix® or Stratix II devices. The
output clock paths from fast PLLs are affected by core and I/O noise because
they don't have their own dedicated power pins. The enhanced PLLs have
their own isolated VCCIO and dedicated path from the PLL to the outputs, thus,
Altera can make accurate jitter measurements. The enhanced PLL jitter specifications can be used as an estimate, but core noise and switching I/O can add to the jitter on the fast PLL outputs. This is design dependent, so Altera cannot guarantee jitter performance for fast PLLs.
Environment
BUILT IN - ARTICLE INTRO SECOND COMPONENT
