Article ID: 000078656 Content Type: Troubleshooting Last Reviewed: 11/04/2013

ECC Enabled Automatically in Cyclone V SoC HPS Devices

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

This problem affects DDR2, DDR3, and LPDDR2 products.

For HPS hard memory controller interfaces in Cyclone V SoC HPS devices, if you create interface widths of 24 or 40, ECC is enabled automatically, but no message is displayed to state that ECC is enabled.

Resolution

The workaround for this issue is simply to be aware that ECC is enabled automatically, with no message displayed.

This issue will be fixed in a future release.

Related Products

This article applies to 1 products

Cyclone® V FPGAs and SoC FPGAs

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