Article ID: 000078653 Content Type: Troubleshooting Last Reviewed: 11/27/2013

IP Compiler for PCI Express SDC Constraint Generates Warnings

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

The following SDC constraint in the automatically generated Synopsys Design Constraints (.sdc) file for the IP Compiler for PCI Express generates warning messages:

set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hissi_pcie_hip* }]

Resolution

This issue has no workaround. You can ignore the warning messages this constraint generates.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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