Article ID: 000078637 Content Type: Troubleshooting Last Reviewed: 07/04/2014

Which clock is the reference clock for HPS Ethernet MDC clock?

Environment

  • Arria® V ST SoC FPGA
  • Arria® V SX SoC FPGA
  • Cyclone® V SE SoC FPGA
  • Cyclone® V ST SoC FPGA
  • Cyclone® V SX SoC FPGA
  • Quartus® II Subscription Edition
  • Ethernet
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    Description

    The correct reference clock for HPS Ethernet clock is l4_mp_clk.

    The V HPS Address Map, emac->gmacgrp->GMII_Address->cr incorrectly states the CSR clock range selection determines the frequency of MDC clock according to l3_sp_clk frequency.

    The correct reference clock for HPS Ethernet clock is l4_mp_clk.

    Resolution This problem will be resolved in a future update to the HPS Address Map.

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