Article ID: 000078637 Content Type: Troubleshooting Last Reviewed: 08/22/2023

Which clock is the reference clock for the HPS Ethernet MDC clock?

Environment

    Quartus® II Subscription Edition
    Ethernet
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Description

The correct reference clock for the HPS Ethernet clock is l4_mp_clk.

The V HPS Address Map, emac->gmacgrp->GMII_Address->cr incorrectly states the CSR clock range selection determines the frequency of the MDC clock according to l3_sp_clk frequency.

 

Resolution

This problem is resolved starting with release 15.1 of the HPS Address Map.

Related Products

This article applies to 5 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA

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