Description
No, it is not possible to perform boundary scan testing over the HPS JTAG pins. However tbe HPS I/O pins do support boundary scan testing through the JTAG pins of the FPGA. The BSDL files generated via the Quartus® II software for Cyclone® V SoC devices will include HPS I/O pins that support boundary scan.
Note: For Cyclone V SoC FPGAs you must power up both the HPS and FPGA to perform a boundary scan test (BST).