Article ID: 000078593 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why are the Avalon byte enables not implemented in my DDR3 UniPHY controller version 11.0?

Environment

    Quartus® II Subscription Edition
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Description

After generating a DDR3 UniPHY controller version 11.0 with the "Enable Avalon-MM byte-enable signal" selected, you may notice that the Avalon byte enable signals are not implemented.

There is a known issue where the "Enable Avalon-MM byte-enable signal" checkbox does not affect the presence or absence of the Avalon byte enables. Instead, the presence or absence of the Avalon byte enables matches the setting of the "Enable DM pins" checkbox under the Memory Parameters tab.

Resolution

The workaround is to use the "Enable DM pins" checkbox to affect the state of the Avalon byte enable signals. Check "Enable DM pins" if you want the Avalon byte enables implemented or uncheck "Enable DM pins" if you do not want the Avalon byte enables implemented.

This issue is fixed in the Quartus® II software version 11.1 and later.

Related Products

This article applies to 8 products

Stratix® V GX FPGA
Stratix® V E FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs
Stratix® IV GT FPGA
Stratix® IV E FPGA

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