Article ID: 000078577 Content Type: Product Information & Documentation Last Reviewed: 02/26/2016

How can I achieve a finer phase step resolution in the Altera_PLL IP if the auto computed resolution is not fine enough, in Stratix V, Arria V and Cyclone V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When using the Altera_PLL IP with Stratix® V, Arria® V and Cyclone® V devices, the Quartus® Prime software will chose the VCO frequency of the PLL based on the user entered input frequency and output frequencies by calculating suitable M and N counter values (fvco=fin*M/N). The VCO frequency consequently determines the achievable phase step resolution for the achievable phase shift values  (phase step resolution = VCO frequency/8). However, the phase step resolution may not be as granular as desired by the user.

Resolution To achieve a finer resolution, the VCO frequency needs to be increased. To do this, use the "Physical Output Enable" option in the Altera_PLL IP and manually enter the M and N counter values to achieve the desired VCO frequency that allows you to achieve your required output frequencies as well as your phase step resolution.

An alternative method would be to set one of the output clocks as very high and to leave this output unconnected. This would force the VCO to be a higher frequency, allowing access to finer phase shift steps.

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This article applies to 15 products

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Arria® V GX FPGA
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Cyclone® V E FPGA
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Cyclone® V SE SoC FPGA
Cyclone® V SX SoC FPGA
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Cyclone® V GX FPGA
Stratix® V GT FPGA

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