Article ID: 000078566 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the Offset Cancellation busy signal de-assertion duration in the ALTGX_RECONFIG block simulation does not match with the duration information in the device handbook?

Environment

  • Stratix® IV GX FPGA
  • Arria® II GX FPGA
  • Stratix® IV GT FPGA
  • Arria® II FPGAs
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Description

Functional and Timing models for ALTGX_RECONFIG block do not reflect the actual duration for the busy signal de-assertion during the Offset Cancellation process.  It is done by design to avoid unneccessary long deadtime in simulation.

This information applies to Stratix® IV GX, Stratix IV GT and Arria® II GX devices.

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