Article ID: 000078560 Content Type: Troubleshooting Last Reviewed: 02/25/2013

Why do I get a pin placement error in Quartus II when assigning a user signal to a dual-purpose configuration data pin that is also used for FPPx16 configuration, even if the dual-purpose pin is reserved to be used as regular IO?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description You may get such a pin placement error in the Quartus® II software if you have also enabled the Partial Reconfiguarion (PR) pins in your project. When the PR pins are enabled, the dual purpose configuration data pins used for 16-bit Fast Passive Parallel (FPPx16) mode can only be used for configuration purposes.
Resolution Disable the PR pins in your project or remove the user signal location assignment to the affected dual-purpose pin. 

Related Products

This article applies to 15 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA