RapidIO II IP Core - VHDL testbench compilation results in an error due to parameter and port type mismatch

When you generate the simulation model VHDL, there are parameter and port type mismatches in the VHDL top level wrapper. Testbench that instantiates the generated top wrapper will provide compilation errors.

Declare the following 1-bit width ports as std_logic instead of std_logic_vector in the VHDL top level wrapper:

• csr_external_tm_mode_wr
• csr_external_mtu_wr
• external_illegal_transaction_decode_set
• external_io_error_response_set
• external_message_request_timeout_set
• external_slave_packet_response_timeout_set
• external_unsolicited_response_set
• external_unsupported_transaction_set
• external_illegal_transaction_target_error_set
• external_missing_data_streaming_context_set
• external_open_existing_data_streaming_context_set
• external_long_data_streaming_segment_set
• external_short_data_streaming_segment_set
• external_data_streaming_pdu_length_error_set
• external_capture_ftype_wr
• external_capture_ttype_wr
• external_letter_wr
• external_mbox_wr
• external_msgseg_wr
• external_xmbox_wr

For V-series FPGA device family variants, change the following ports in the top level generated wrapper as std_logic_vector(0 downto 0) to match with the respective SystemVerilog vector port defined in module altera_rapidio2_top:

• pll_locked
• pll_powerdown

For parameter type mismatch error, you can safely remove the parameter SYS_CLK_FREQ in the generated top wrapper. IP core will not further process on this parameter.