Article ID: 000078524 Content Type: Troubleshooting Last Reviewed: 08/22/2023

Why do I see invalid read data when the DSP Builder memory interface bus has an NCO or FIR attached?

Environment

    Quartus® II Subscription Edition
    DSP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see invalid read data at the end of a memory read burst or at the end of any single memory read if you have an NCO or FIR component on your DSP Builder memory interface bus.

Resolution

This is due to a problem with the Quartus® II software.

The workaround is to move the NCO or FIR filter to a non-zero address.

This is scheduled to be fixed in a future release of the Quartus® II software.

Related Products

This article applies to 20 products

Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Intel® Arria® 10 GT FPGA
Stratix® IV E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Arria® V GT FPGA
Stratix® IV GX FPGA
Intel® Arria® 10 GX FPGA
Stratix® IV GT FPGA
Cyclone® V E FPGA
Intel® Arria® 10 SX SoC FPGA

1