Description
Due to a problem in the XAUI PHY IP core, the embedded Synopsys Design Constraint (SDC) is missing a false path for the paths from tx_reset_n to reset_tx_clk_n_meta/reset_tx_clk_n.
In the XAUI PHY IP core, tx_reset_n node is synchronized to a new clock domain through two registers: reset_tx_clk_n_meta and reset_tx_clk_n and is thus a false path.
Resolution
You can ignore the recovery/removal path violations reported by TimeQuest. Alternatively you can apply a set_false_path constraint on these paths in your SDC file.
