Article ID: 000078513 Content Type: Troubleshooting Last Reviewed: 04/18/2023

Why is the phase_done deassertion inconsistent in RTL simulation?

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When using dynamic phase stepping in the Altera_PLL mega function, you may see different behavior for the de-assertion of the phase_done output signal in RTL simulation.

The correct behavior is for phase_done to de assert on the rising edge of scanclk as stated in AN 661: Implementing Fractional PLL Reconfiguration with Altera_PLL and Altera_PLL_RECONFIG Megafunctions (PDF).

However, in RTL simulation, you may see phase_done de assert at the falling edge of scanclk.  This typically occurs only in the first phase step operation.  This is a problem in the RTL simulation model.

Resolution

This issue with the RTL simulation model is fixed in version 13.1 of the Quartus® II software.

Related Products

This article applies to 15 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.