Timing violation when enable 'Extra Timing Report Clock' in DDR3 UniPHY-based controller

You might see timing violation when you disable the DQS tracking in the DDR3 controller following the steps in this knowledge article:

Why has the option "Enable read DQS tracking" in UniPHY-based DDR3 SDRAM IP changed between Quartus® II software releases?

The timing violation happens when the controller is named with the string “controller“.   

The workaround for this problem is by changing the string “controller” to “alt*controller” in <instance>_p0_report_timing_core.tcl

Change:

if { ! } {
        set controller_regs [get_registers |*controller_*inst|*]
        set inst_other_if
    } else {
        set controller_regs [get_registers |*:*controller_*inst|*]
        set inst_other_if
    }

To:

if { ! } {
        set controller_regs [get_registers | *alt*controller_*inst|*]
        set inst_other_if
    } else {
        set controller_regs [get_registers |*:* alt*controller _*inst|*]
        set inst_other_if
    }

This problem is fixed starting with the Quartus® II software version 13.1.