Article ID: 000078460 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Are there any known issues with DDR2 High Performance Controller On Chip Termination Timing in Full Rate Mode when performing Read to Write transactions that could result in missing DQS edges from a Write transaction that directly follows a Read?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, there is a known issue with DDR2 OCT in the Quartus® II software and IP version 8.1 and earlier of the DDR2 SDRAM High Performance (HP) Memory controller in Stratix® III, Stratix IV GX and Stratix IV E devices that could cause the first Write following a Read to be corrupted.

    This issue also effects DDR2 Altmemphy IP version 8.1 and earlier when configured for Full Rate with Dynamic Termination turned ON.

    The issue is due to an OCT timing failure that may cause bus contention in some low latency configurations.

    The issue manifests itself by causing Write DQS strobe edges to be missing from the write transaction that directly follows the previous read. Typically 6 DQS edges are observed as opposed to the expected 8.

    A software patch is available for QuartusII software version 8.1 and should be obtained by filing a Support Request via mysupport.

    The issue is fixed in a Quartus II software and IP version 9.0.

    Related Products

    This article applies to 3 products

    Stratix® IV GX FPGA
    Stratix® III FPGAs
    Stratix® IV E FPGA