Article ID: 000078427 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Do Cyclone IV GX devices support single-ended reference clock support in IO Bank 3B and 8B?

Environment

  • Cyclone® IV GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Single-ended REFCLK/DIFFCLK positive pins from bank 3B or bank 8B cannot be routed to the FPGA core. This is because there is no routing path exists between the clock pins and FPGA core. You will see fitter error from Quartus®  II software if above pin assignment is added in the design.

Single-ended REFCLK/DIFFCLK positive pins can be routed only to MPLL5, MPLL6, MPLL7 and MPLL8, when these PLLs are used for non-transceiver applications.

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