Article ID: 000078402 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How can I assign a PLL output clock to a Global Clock Network?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You can assign a PLL output clock to a Global Clock Network by using Quartus® II software Assignment Editor or define it in your .qsf file. 

    Follow the steps below to make the assignment:in the Assignment Editor:

    1) Create a new assignment in the Assignment Editor and then set:

    • Assignment Name = Global Signal
    • Value = Global Clock 
    • Enabled =Yes 
    • To = <node name> (For example, use the node finder to locate the node name of the PLL output clock such as "pll1:inst|altpll:altpll_component|pll1_altpll:auto_generated|wire_pll1_clk[0]")

    2) After the assignment is created, the assignment list will be updated.

    3) Recompile the design. 

    4) After compilation, verify your assignment by viewing the "Global and other fast signals" report under Fitter > Resource Section > Global & Other fast signals. You will see that the output clock is now connected to a Global Clock.

    When entering an assignment in the .qsf file follow these steps:

    1) Open the .qsf file and add the following:

    set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "<node name>"      

    2) Recompile the design. 

    3) After compilation, verify your assignment by viewing the "Global and other fast signals" report under Fitter > Resource Section > Global & Other fast signals. You will see that the output clock is now connected to a Global Clock.

    Related Products

    This article applies to 1 products

    Stratix® IV GX FPGA

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